1. Field of the Invention
The present invention relates to a tester for semiconductor integrated circuits, and more specifically to a tester for testing semiconductor integrated circuits comprising an A/D converter circuit to convert analog signals to digital signals, and a D/A converter circuit to convert digital signals to analog signals.
2. Background Art
The tester for semiconductor integrated circuit is called simply a tester. In recent years, in a system LSI constituted as a one-chip semiconductor integrated circuit constituted by a plurality of functionally systematized modules (1-chip LSI) or a hybrid integrated circuit in which chips of a plurality of circuits are combined (chip-set LSI), integration by combining high-performance, high-accuracy digital circuits and analog circuits (mixed-signalization) is being progressed rapidly, the testers for these semiconductor integrated circuits to cope with this mixed-signalization is also being progressed rapidly, and testers for testing mixed signal semiconductor integrated circuits are provided from tester manufacturers.
However, in order to accommodate the high-performance specifications of the mixed signal semiconductor integrated circuits, the testers tend to be expensive. Under such a situation, there has been a movement to avoid increase in the cost of tester through the reuse of existing low-speed, low-accuracy testers used, for example, for logic LSIs.
A significant problem to be solved in such testers is the test of D/A converter circuits to convert digital signals to analog signals and A/D converters to convert analog signals to digital signals. With increase in accuracy of these converter circuits, the problem is how to realize testers for semiconductor integrated circuits comprising these converter circuits at low cost.
In a general test circumstance for testers, along a measurement path from the measuring instrument inside the tester to the semiconductor integrated circuit to be tested (hereafter called DUT), there are a plurality of jigs to connect between the tester and the DUT such as a probe card, a test circuit board such as a DUT board and cables, and the measurement path is long, causing noise to occur and measurement accuracy to be reduced, and it is difficult to test of plurality of the DUT at a time. Also, since a low-speed tester cannot test the DUT at a practical speed due to the restriction, increase in testing time for testing mass-produced DUTs is concerned.
Japanese Patent Laid-Open No. 1-316024 proposes a tester comprising a memory element for storing converted data in the address specified by input data to the D/A converter of the testing circuit, in which D/A converted analog signals are inputted to the A/D converter, the outputs of the A/D converter are sequentially stored in the memory element, the converted data stored in the memory element are sequentially transmitted to the tester when all the inputted data have been converted, and the inputted data are sequentially compared with the converted data in the tester.
However, since the inputted data to the D/A converter, the addresses of the memory element for storing converted data, and the control signals must be supplied from the tester, and furthermore, since the data stored in the memory element must be supplied to the tester, the measurement accuracy may be lowered due to noise in the long measurement path between the DUT and the tester. Also due to the occupation of the number of tester pin electronics, the simultaneous measurement of more than one DUT is difficult. Furthermore, since communication to transmit converted data to the tester takes much time, and the test results are judged after all the tests have been completed, the reduction of time is also difficult.
Although the inventors of the present application filed the invention enabling the above-described problems to be solved on Nov. 22, 2000, as Japanese Patent Application No. 2000-356724, the test assisting device known as BOST was still large in the invention of the prior application, and further improvement was required so as to be installed in the space in the vicinity of the testing circuit board.
The present invention proposes a tester for semiconductor integrated circuits that can realize high-speed, high-accuracy measurement at low costs using a test assisting device that can be installed in a smaller space.
The present invention also proposes a method for testing semiconductor integrated circuits that can realize high-speed, high-accuracy measurement at low costs using a test assisting device that can be installed in a smaller space.
According to one aspect of the present invention, a tester for semiconductor integrated circuits comprises a testing circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested, a test assisting device disposed in the vicinity of and connected to the testing circuit board; and a test machine connected to the test assisting device. The semiconductor integrated circuit to be tested comprises an A/D converter circuit to convert analog signals to digital signals, and a D/A converter circuit to convert digital signals to analog signals. The test assisting device has a data circuit, a testing D/A converter circuit, a testing A/D converter circuit, a measured data memory, and an analyzer portion. The data circuit generates digital test signals and supplies the test signals to the D/A converter circuit of the semiconductor integrated circuit to be tested. The testing D/A converter circuit converts digital test signals from the data circuit to analog test signals and supplies the test signals to the A/D converter circuit of the semiconductor integrated circuit to be tested. The testing A/D converter circuit converts analog test outputs of the D/A converter circuit of the semiconductor integrated circuit to be tested to digital test outputs. The measured data memory stores the digital test outputs from the A/D converter circuit of the semiconductor integrated circuit to be tested and the digital test outputs of the testing A/D converter circuit. The analyzer portion analyzes each of the digital test outputs stored in the measured data memory. These data circuit, testing D/A converter circuit, testing A/D converter circuit, measured data memory, and analyzer portion are constituted so as to be separately provided on a plurality of circuit boards. The tester for semiconductor integrated circuits is constituted so as to supply the test signals containing the digital test signals and the analog test signals to the semiconductor integrated circuit to be tested based on instructions from the test machine. The tester supplies the results of analysis of each digital test output stored in the measured data memory by the analyzer portion to the test machine.
According to another aspect of the present invention, a tester for semiconductor integrated circuits comprises a testing circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested, a test assisting device disposed in the vicinity of and connected to the testing circuit board; and a test machine connected to the test assisting device. The semiconductor integrated circuit to be tested comprises an A/D converter circuit to convert analog signals to digital signals, and a D/A converter circuit to convert digital signals to analog signals. The test assisting device has a data circuit, a testing D/A converter circuit, a testing A/D converter circuit, a measured data memory, an analyzer portion, a first circuit board, a second circuit board, and a third circuit board. The data circuit generates digital test signals and supplies the test signals to the D/A converter circuit of the semiconductor integrated circuit to be tested. The testing D/A converter circuit converts digital test signals from the data circuit to analog test signals and supplies the test signals to the A/D converter circuit of the semiconductor integrated circuit to be tested. The testing A/D converter circuit converts analog test outputs of the D/A converter circuit of the semiconductor integrated circuit to be tested to digital test outputs. The measured data memory stores the digital test outputs from the A/D converter circuit of the semiconductor integrated circuit to be tested and the digital test outputs of the testing A/D converter circuit. The analyzer portion analyzes each of the digital test outputs stored in the measured data memory. The first circuit board carries at least the testing D/A converter circuit and the testing A/D converter circuit. The second circuit board carries at least the measured data memory. The third circuit board carries the analyzer portion. The tester for semiconductor integrated circuits is constituted so as to supply the test signals containing the digital test signals and the analog test signals to the semiconductor integrated circuit to be tested based on instructions from the test machine. The tester supplies the results of analysis of each digital test output stored in the measured data memory by the analyzer portion to the test machine.
According to another aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit to be tested. The semiconductor integrated circuit comprises an A/D converter circuit to convert analog signals to digital signals, and a D/A converter circuit to convert digital signals to analog signals. The method uses a test assisting device disposed in the vicinity of a testing circuit board to transmit signals to and receive signals from a semiconductor integrated circuit to be tested. The test assisting device has a data circuit, a testing D/A converter circuit, a testing A/D converter circuit, a measured data memory, and an analyzer portion. The data circuit generates digital test signals and supplies the test signals to the D/A converter circuit of the semiconductor integrated circuit to be tested. The testing D/A converter circuit converts digital test signals from the data circuit to analog test signals and supplies the test signals to the A/D converter circuit of the semiconductor integrated circuit to be tested. The testing A/D converter circuit converts analog test outputs of the D/A converter circuit of the semiconductor integrated circuit to be tested to digital test outputs. The measured data memory stores the digital test outputs from the A/D converter circuit of the semiconductor integrated circuit to be tested and the digital test outputs of the testing A/D converter circuit. The analyzer portion analyzes each of the digital test outputs stored in the measured data memory. These data circuit, testing D/A converter circuit, testing A/D converter circuit, measured data memory, and analyzer portion are constituted so as to be separately provided on a plurality of circuit boards. The method supplies the test signals containing the digital test signals and the analog test signals to the semiconductor integrated circuit to be tested based on instructions from the test machine. The method supplies the results of analysis of each digital test output stored in the measured data memory by the analyzer portion to the test machine.
A tester of a semiconductor integrated circuit according to the present invention, as described above, since the test assisting device disposed in the vicinity of the testing circuit board is provided with a data circuit, a testing D/A converter circuit, a testing A/D converter circuit, a measured data memory, and a DSP analyzing portion; the test assisting device is made to conduct the A/D converter circuit and the D/A converter circuit of a semiconductor integrated circuit to be tested; and in addition, the test assisting device is constituted separately on a plurality of circuit boards; the test of a mixed-signal-type semiconductor integrated circuit comprising an A/D converter circuit and a D/A converter circuit can be conducted at high accuracy and high speed, and the cost reduction of the tester can be achieved, the test assisting device can be installed in a small space, and the space for testing is saved.
Also according to the tester using a first circuit board carrying at least a D/A converter circuit for testing and an A/D converter circuit for testing, a second circuit board carrying at least a measured data memory, and a third circuit board carrying at least a analyzing portion, the test at high accuracy and high speed can be conducted, and the price can be reduced. In addition, since the test assisting device is divided on at least three circuit boards, the test assisting device can be installed in a small space, and the space can be saved.
Other and further objects, features and advantages of the invention will appear more fully from the following description.